My Telecommunications client is looking for an ASICS Engineer to join them on an initial 6 month basis working fully remote Inside IR35.
Client Details
My Telecommunications client is based in London and are a global firm who are industry leaders and are looking for a skilled ASICS Engineer to develop Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments.
Description
Your main responsibilities will include but will not be limited to:
- Implementing Verification Methodologies: Utilising UVM (Universal Verification Methodology) and Formal Verification techniques.
- Creating Testbenches and Verification Components: Developing UVCs (Universal Verification Components), C models, and reusable verification environments (both vertical and horizontal).
- Formulating Test Plans: Based on design documents and collaborating with design and systems engineers.
- Writing and Debugging Assertions: Crafting and troubleshooting SystemVerilog assertions.
- Analysing Coverage Data: Evaluating coverage metrics and collaborating with design teams to resolve coverage gaps.
- Enhancing Regression Frameworks: Developing or improving frameworks for running regression tests.
- Conducting Power-Aware Simulations: Executing and debugging simulations with UPF (Unified Power Format).
- Resolving Regression Failures: Debugging issues with the design and systems teams.
- Automating with Python/Perl: Implementing scripts to streamline workflows and boost team efficiency.
- Providing Debug Support: Assisting software and other teams with debugging tasks.
- Documenting Processes: Maintaining comprehensive documentation of verification processes and methodologies.
Profile
The successful candidate will have the following experience:
- Design and Verification Expertise: Extensive experience in designing and verifying SoCs (System-on-Chip) and employing SoC methodologies to validate complex units using industry-standard tools and technologies.
- Proficient in Test Bench Development: Skilled in creating unit and subsystem-level test benches utilising SV/UVM (SystemVerilog/Universal Verification Methodology).
- Verification Techniques: Expertise in constrained random testing and metrics-driven verification.
- C Model Integration and Scoreboarding: Experienced in integrating C models and implementing scoreboarding techniques.
- Firmware Integration Verification: Knowledgeable in verifying firmware code integration.
- AMBA Protocols and Bus Interconnects: Proficient in functional and formal verification of AMBA protocols and bus interconnects, with a focus on coverage closure.
- Power-Aware and Clock Domain Crossing Verification: Experienced in power-aware verification and clock domain crossing analysis.
- Debugging Skills: Adept at debugging test failures and resolving issues effectively.
- Verification Planning and Techniques: Strong understanding of verification planning, coverage analysis, and the application of pseudo-random and constrained random techniques, as well as assertion-based and formal verification methods using SystemVerilog.
- Programming and Scripting Skills: Proficient in Verilog, C/C++, SystemC, and TCL/Perl/shell scripting.
- Analytical and Team Skills: Possesses strong analytical abilities and thrives in dynamic, fast-paced team environments.
- Communication Skills: Excellent communication skills, both verbal and written.
Job Offer
On offer for a successful candidate is the ability to work fully remote on a 6 month contract while receiving a day rate inside IR35 which is in-line with market expectations.