Timing Constraints / Synthesis:
Candidate will be responsible for developing synthesis/timing constraints for subsystems and for chip top, setup synthesis flow, run synthesis on the design, fix issues and optimize the constraints and other inputs to ensure good quality synthesis results.
- 5+ years of hands-on experience in RTL synthesis, equivalence checking
- Good understanding of structural Verilog and in-depth expertise on understanding choice of library/cells in synthesis output.
- Constraints development and management of multi partition design and top level constraints
- Understanding of timing budgeting and being able to work with Front End RTL team to refine constraints
- Experience in analysis of timing paths to identify key issues in levels of logic and partitioning at synthesis stage
- Experience in debugging non-equivalent and abort points in FEV runs.
- Automation Skills using scripting languages like TCL/PERL/Python/SHELL